I. Field of the Disclosure
The technology of the disclosure relates generally to memory systems and memory pre-decoder circuits.
II. Background
Memory pre-decoder circuits are employed to pre-decode portions of memory addresses prior to final decoding by a decoder. For example, a memory pre-decoder circuit may pre-decode a portion of a memory address that identifies a row of memory cells in memory. The pre-decoded portion of the memory address can be provided to a corresponding row decoder. The row decoder selects the row in memory based on the pre-decoded portion of the memory address from the memory pre-decoder circuit.
A generalized example of a memory pre-decoder circuit 10 is shown in FIG. 1A. FIG. 1B illustrates a specific example of the memory pre-decoder circuit 10 shown in FIG. 1A. The memory pre-decoder circuit 10 is configured to receive a memory address input 12 from a CPU core (not shown). The memory address input 12 in FIGS. 1A and 1B is a single bit of a memory address. However, it should be noted that additional memory pre-decoder circuits are typically provided, in parallel to pre-decode different portions of the memory address from the CPU core.
If the CPU core is powered in a lower voltage domain, the memory address input 12 is received by the memory pre-decoder circuit 10 in the lower voltage domain. However, memory systems, such as SRAM, DRAM, ROM, EPROM, EEPROM, etc., are generally powered by a higher voltage to be provided in a higher voltage domain. This allows the memory system to maintain a threshold voltage and preserve the integrity of data stored in the memory cells. Accordingly, the memory pre-decoder circuit 10 includes a voltage level shifter 14 that level shifts the memory address input 12 into the higher voltage domain. After being level shifted into the higher voltage domain, a level shifted memory address input 12(1) is then provided to a latch 16 clocked by a latch clock signal 18. In FIG. 1B, the latch clock signal 18 is actually received as a latch clock signal 18(1) and an inversion of the latch clock signal 18(1) is received as a latch clock signal 18(2). The level shifted memory address input 12(1) is then latched in accordance with the latch clock signal 18(1) and the latch clock signal 18(2) to provide a latched memory address input 12(2) in the higher voltage domain. The latch clock signal 18 and the latch clock signal 18(1) may be received as a system clock from the CPU core.
A memory pre-decoder 20 receives the latched memory address input 12(2) from the latch 16. In addition, as shown in FIG. 1B, the memory pre-decoder 20 receives another latched memory address input 12(3) in the higher voltage domain from another latch (not shown). The memory pre-decoder 20 then generates a pre-decoder output 22 based on the latched memory address input 12(2) and the other latched memory address input 12(3). The pre-decoder output 22 from the memory pre-decoder 20 is then provided to an output driver 24. The output driver 24 generates a gated pre-decoder output 36 to a final downstream decoder (not shown). The output driver 24 needs to gate the pre-decoder output 22 due to the propagation delay from the latch 16 to the output driver 24. More particularly, the output driver 24 cannot be clocked by the system clock (latch clock 18(1)). Rather, the output driver 24 is clocked by a root clock signal 38 as a result of the propagation delay. The root clock signal 38 must be delayed with respect to the system clock (latch clock 18(1)) by at least the propagation delay from the latch 16 to the output driver 24. Thus, this propagation delay must be part of the setup time.
Additionally, other gated pre-decoder outputs (not shown) may be transmitted to the final downstream decoder from other parallel output drivers shown). Since the voltage level shifter 14, the latch 16, and the memory pre-decoder 20 must setup the signal level of the pre-decoder output 22 before the output driver 24 can generate the gated pre-decoder output 36, the voltage level shifter 14, the latch 16, and the memory pre-decoder 20 are provided in a memory pre-decode setup path 40 of the memory pre-decoder circuit 10. Considering that the gated pre-decoder output 36 is generated in accordance with the root clock signal 38, the setup time delay resulting from the memory pre-decode setup path 40 is included in the overall setup time required for accessing memory.
As further shown in FIG. 1B, once the gated pre-decoder output 36 has been setup and the root clock signal 38 generates the gated pre-decoder output 36, another access delay of two gates is needed by the output driver 24. Furthermore, the memory pre-decode setup path 40 of the memory pre-decoder circuit 10 provides one gate for an input buffer in the voltage level shifter 14, two gates for level shifting circuitry of the voltage level shifter 14, two gates for the latch 16, and two gates for the memory pre-decoder 20. Increased setup time increases memory access times and slows down memory. Therefore, it may be desirable to reduce the setup time in the memory pre-decode setup path 40 of the memory pre-decoder circuit 10. Providing faster access to memory can increase the performance speed of computer-based devices.